CVE-2026-23554

What it is

The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.

At a glance

Exploitability

Can be exploited locally on the machine with a low-privilege account. High risk of data exposure, data tampering, service disruption.

Exploit odds

0.1% chance of exploitation in the next 30 days (EPSS).

Fix

A patch, advisory or fixed version is referenced. Upgrade or apply it.

Timeline

1. 2026-03-23 07:16 UTC PublishedDisclosed publicly on CVE.org and NVD
2. 2026-06-17 10:21 UTC Last updatedMost recent change to the record

Details

Published

2026-03-23 07:16 UTC

Last modified

2026-06-17 10:21 UTC

Exploit probability

0.1% · EPSS, next 30 days

Weakness

CWE-367

Record status

Analyzed

Affected

• Xen

Attack profile CVSS 3.1 · 7.8

Attack vector

Local

Complexity

High

Privileges needed

Low

User interaction

None

Scope

Changed

Confidentiality

High

Integrity

High

Availability

High