CVE-20XX-?
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CVE-2026-12629

4.6 MEDIUM 0.2% exploit odds Fix listed Denial of service OS & kernel

What it is

The ARM PL011 UART driver in drivers/serial/uart_pl011.c fails to acknowledge receive error interrupts. On the PL011, the framing, parity, break, and overrun error interrupts (PL011_IMSC_ERROR_MASK) are cleared only by writing the interrupt-clear register UARTICR; reading the data register clears the RX interrupt and the per-byte RSR status but not the error interrupt status in MIS. The interrupt service routine pl011_isr() acknowledged only the CTS modem-status interrupt and never wrote icr for the error bits, so an asserted error interrupt remains pending after the ISR returns. When an application enables error-interrupt reporting via the public uart_irq_err_enable() API, an attacker who controls the serial peer can deterministically assert these error bits by injecting line errors on the RX line — a baud/stop-bit mismatch or mid-character break (framing/break error), a flipped parity bit (parity error), or FIFO flooding (overrun error). Because the error interrupt is never cleared, the interrupt line stays asserted and the CPU re-enters pl011_isr() immediately and indefinitely, producing an interrupt-storm livelock from which the core makes no forward progress. The impact is an availability-only denial of service (permanent hang), reachable from an external or removable UART peer. Exploitation is gated by configuration: the error interrupt is off by default and no in-tree subsystem enables it, so only applications that explicitly call uart_irq_err_enable() on a PL011-based, interrupt-driven port are affected. The fix makes pl011_isr() acknowledge the pending error bits via uart->icr, breaking the loop, and additionally clears the latched RSR status in pl011_err_check().

At a glance

Exploitability
Can be exploited with physical access without logging in. High risk of service disruption.
Exploit odds
0.2% chance of exploitation in the next 30 days (EPSS).
Fix
A patch, advisory or fixed version is referenced. Upgrade or apply it.

Timeline

  1. PublishedDisclosed publicly on CVE.org and NVD
  2. Last updatedMost recent change to the record

Why it ranks here

Details

Published
Last modified
Exploit probability
0.2% · EPSS, next 30 days
Weakness
CWE-835
Record status
Awaiting Analysis

Attack profile CVSS 3.1 · 4.6

Attack vector
Physical
Complexity
Low
Privileges needed
None
User interaction
None
Scope
Unchanged
Confidentiality
None
Integrity
None
Availability
High
Raw vector

CVSS:3.1/AV:P/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:H

Is it in your code?

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Fix and advisories

References

NVD record · CVE.org record